A processor may include one or more processing cores, caches, and cache controllers. The cache controllers are circuit logics used to manage caches for read and write operations directed to a main memory. Caches may include different types of caches including L1, L2, and L3 caches. An L1 cache is a cache associated with a specific processing core. An L2 cache may be shared by several cores in a multicore processor. Further, multiple processors may share a common L3 cache. Each cache may include one or more cache entries to store local copies of data stored in the main memory and the addresses of the data stored in the main memory. The cache controllers of the processor may manage operations on L1, L2, and L3 caches according to a cache coherence protocol. The cache coherence protocol is a set of rules that ensures consistency of data stored in multiple caches and the main memory.